Joint Test Action Group (JTAG) refers to the IEEE 1149 standard for test access ports for testing printed circuit boards using boundary scan. JTAG is used by Automated Test Generation (ATG) tools to test printed circuit boards. Boundary Scan Description Language (BSDL) has been developed as part of the IEEE 1149.1 standard for board-level JTAG and, further, Hierarchical Scan Description Language (HSDL) has been developed as an extension of BSDL. BSDL/HSDL describe resources available on a board or a component of a board (where HSDL describes components composed of other components). While BSDL/HSDL is efficient for board-level JTAG, passage from board-level JTAG to chip-level JTAG highlights limitations of BSDL/HSDL.
Instruction JTAG (IJTAG) is being standardized (denoted as the P1687 standard) to overcome existing JTAG limitations associated with the move from board-level JTAG to chip-level JTAG; however, ongoing work associated with IJTAG has revealed that BSDL/HSDL is unable to satisfy description requirements for chip-level JTAG testing. BSDL/HSDL relies on an ordered list of cells composing the boundary scan register, however, such a static description is not suited to describe complex dynamic scan chains required in IJTAG. Furthermore, BSDL/HSDL fails to provide any space for describing test procedures needed for each component of the system.